Distributed digital systems, or DDS's, are generally known. DDS's are employed in digital systems such as digital oscilloscopes, logic analyzers, and digital telecommunications systems to name but a few. A DDS usually comprises a network of digital modules interconnected by signal transmission lines such as cabling, printed circuit traces, etc. The modules are generally devices such as microcomputers, voltmeters, D/A and/or A/D converters, multichannel data acquisition units, digital word generators, processing circuitry etc., as well as submodules within such devices.
It is frequently imperative that the modules of the DDS be synchronized so that they are triggered simultaneously by some event originating either on one of the modules or externally of one or more of the modules, e.g., by pulses from a master clock. For simplicity, the example of a master clock will be employed in connection with the following description, but it is to be understood that this is for explanatory purposes only and that the invention described herein is not limited thereto. The invention has application to any DDS where the modules are intended to be simultaneously responsive to an external event, including, by way of example, enable and/or inhibit signals, sample signals, set and/or reset signals and the like, and the example of the master clock is applicable to thereto. Thus, as used herein, reference to master clock pulses is intended to encompass such signals.
Typically, master clock pulses are generated somewhere in (or even externally of) the DDS and transmitted over a transmission line to the various modules. In state of the art DDS's, master clock pulses in the gigahertz range are common. This has given rise to problems not present, or less significant, in DDS's operating at lower frequencies. For example, transmission of such high frequency master clock pulses requires specially designed high frequency transmission lines that add to the complexity and expense of the DDS. Additionally, the terminal impedance of the transmission line is not precisely controllable and often causes an impedance mismatch at high frequencies. Moreover, discontinuities may appear on the transmission line at high frequencies. Impedance mismatches and discontinuities can cause reflections of incident master clock pulses to appear on the transmission line. As the master clock frequency increases, and as the module spacing increases, the reflections may increasingly interfere with and/or distort the incident master clock pulses. Since the magnitude of a reflected signal at any point along a transmission line is a function of the location and severity of the impedance mismatch/discontinuity which caused it, the resultant clock pulses received by a particular module may be changed enough to cause that module to be less accurately synchronized with the other modules of the DDS.
It is therefore desirable to provide a method and apparatus in which the modules of a DDS remain synchronized at high frequency operation even in the presence of impedance mismatches and/or discontinuities on the transmission line carrying the master clock pulses (or signals indicative of some event) to which the modules are to be synchronized. It is also desirable that such method and apparatus be simple in design and easy and economical to implement. The present invention achieves these goals.